VLSI viva compilation

All the below stuff is a compiled post from google of all the viva questions asked on vlsi and avlsi , do take a look  I've actually made this for me :P ( Last minute Reading Stuff :) ;) )

1. Why does the present VLSI circuits use MOSFETs instead of BJTs?

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.

2. What are the various regions of operation of MOSFET? How are those regions used?

MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.

3. What is threshold voltage?

The value of voltage between Gate and Source i.e. V_GS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called threshold voltage (V_t is positive for NMOS and negative for PMOS).

4. What does it mean "the channel is pinched off"?

For a MOSFET when V_GS is greater than V_t, a channel is induced. As we increase V_DS current starts flowing from Drain to Source (triode region). When we further increase V_DS, till the voltage between gate and channel at the drain end to become V_t, i.e. V_GS - V_DS = V_t, the channel depth at Drain end decreases almost to zero, and the channel is said to be pinched off. This is where a MOSFET enters saturation region.

5. Explain the three regions of operation of a MOSFET.

Cut-off region: When V_GS < V_t, no channel is induced and the MOSFET will be in cut-off region. No current flows.
Triode region: When V_GS ≥ V_t, a channel will be induced and current starts flowing if V_DS > 0. MOSFET will be in triode region as long as V_DS < V_GS - V_t.
Saturation region: When V_GS ≥ V_t, and V_DS ≥ V_GS - V_t, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when V_DS is further increased.

6. What is channel-length modulation?

In practice, when V_DS is further increased beyond saturation point, it does has some effect on the characteristics of the MOSFET. When V_DS is increased the channel pinch-off point starts moving away from the Drain and towards the Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length Modulation.

7. Explain depletion region.

When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.

8. What is body effect?

Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all MOSFETs the body substrate is connected to the most negative power supply (in case of PMOS most positive power supply). Which causes a reverse bias voltage between source and body that effects the transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel depth to its normal depth the VGS has to be increased. This is effectively seen as change in the threshold voltage - V_t. This effect, which is caused by applying some voltage to body is known as body effect.

9. Give various factors on which threshold voltage depends.

As discussed in the above question, the V_t depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of V_t decreases by about 2mV for every 1^oC rise in temperature.

Q. Why are PMOS transistor networks generally used to produce high (i.e. 1) signals, while NMOS networks are used to product low (0) signals?

PMOS is used to drive 'high' because of the thresholdvoltage-effect The same is true for NMOS to drive 'low'.

A NMOS device cant drive a full '1' and PMOS cant drive full '0'Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing

Q. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates) usually limited to four?

To limit the height of the stack.

As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be.

Q. In an IC layout, what is a polygon and what is a path? What are the
advantages and disadvantages of each?

A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it's off grid with 45 degree angle. Polygon is always on-grid, unless it's a copy and flip. However, polygon is hard to edit and work with.

Q. What is the difference between a contact and a via? What is a "stacked" via process?

Via: a contact between two conductive layers.
Contact:Opening in an insulating film to allow contact to an underlying electronic device.
The placement of vias directly over the contacts or other,lower vias is known as stacked via.

Q. Why must transistors be provided with "bulk" connections? What voltage
levels are connected to a p-type substrate and an n-type well through these
connections

To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit

Q. A computerized self-diagnostic for a ROM test uses:

A. the check-sum method

Q. How many storage locations are available when a memory device has twelve address lines?

 4096

Q. Which of the following memories uses a MOSFET and a capacitor as its memory cell?

DRAM

Q. Which of the following best describes nonvolatile memory?

memory that retains stored information when electrical power is removed

Q. The access time (tacc) of a memory IC is governed by the IC's:

internal address decoder

Q. Select the best description of read-only memory (ROM).

nonvolatile, used to store information that does not change during system operation

Q. Advantage(s) of an EEPROM over an EPROM is (are):

 the EEPROM can erase and reprogram individual words without removal from the circuit

Q. A nonvolatile type of memory that can be programmed and erased in sectors, rather than one byte at a time is:

flash memory

Q. Which of the following best describes static memory devices?

 semiconductor memory devices in which stored data is retained as long as power is applied

Q. What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero?

Static power dissipation in CMOS is due to leakage currents like reverse biased source bulk junction, drain bulk junction currents and CMOS operated in sub threshold regions.Static power is negligible not zero and comes into play (becomes dominant over dynamic power) when switching speed of CMOS is less.

Dynamic power dissipation is due to when both PMOS and NMOS during swithing coincides (in characteristics) at a common point where short circuit exist between power supply and ground for nano second.That is cause of dynamic power dissipation and it increases with switching frequency.Static power has value close to zero in comparison of dynamic power during high switching frequency.

What is metastability?

When setup or hold window is violated in an flip flop then signal attains a unpredictable value or state known as metastability

How chance of metastable state failure can be reduced?

Lowering clock frequency

Lowering data speed

Using faster flip flop

What are the advantages of using synchronous reset ?

No metastability problem with synchronous reset (provided recovery and removal time for reset is taken care).Simulation of synchronous reset is easy.

What are the disadvantages of using synchronous reset ?

Synchronous reset is slow.

Implementation of synchronous reset requires more number of gates compared to asynchronous reset design.

An active clock is essential for a synchronous reset design. Hence you can expect more power consumption

What are the advantages of using asynchronous reset ?

Implementation of asynchronous reset requires less number of gates compared to synchronous reset design.

Asynchronous reset is fast.

Clocking scheme is not necessary for an asynchronous design. Hence design consumes less power. Asynchronous design style is also one of the latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities.

What are the disadvantages of using asynchronous reset ?

Metastability problems are main concerns of asynchronous reset scheme (design).

Static timing analysis and DFT becomes difficult due to asynchronous reset.

In a system with insufficient hold time, will slowing down the clock frequency help?

No.

Making data path slower can help hold time but it may result in setup violation

In a system with insufficient setup time, will slowing down the clock frequency help?

Yes.

Making data path faster can also help setup time but it may result in hold violation

Cross talk can be avoided by ___.Shielding the nets

Leakage power is inversely proportional to ___.Threshold Voltage

To avoid cross talk, the shielded net is usually connected to ___VSS

If the data is faster than the clock in Reg to Reg path ___ violation may come. Hold

Difference between Clock buff/inverters and normal buff/inverters is __Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters

Which configuration is more preferred during floorplaning ? Double back with flipped rows